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www.gennum.com gs1528a / GS9068A hd-linx? ii multi-rate dual slew-rate cable driver gs1528a / GS9068A data sheet 30953 - 4 january 2006 1 of 16 features gs1528a ? smpte 292m, smpte 344m and smpte 259m compliant ? dual coaxial cable driving outputs with selectable slew rate ?50 differential pecl input ? pb-free and rohs compliant ? pin compatible with GS9068A hd-linx ii sd sdi cable driver ? seamless interface to other hd-linx ii family products ? single 3.3v power supply operation ? operating temperature range: 0c to 70c GS9068A ? smpte 259m and smpte 344m compliant ? dual coaxial cable driving outputs ?50 differential pecl input ? pb-free and rohs compliant ? pin compatible with gs152 8a hd-linx ii multirate sdi dual slew-rate cable driver ? seamless interface to other hd-linx ii family products ? single 3.3v power supply operation ? operating temperature range: 0c to 70c applications gs1528a ? smpte 292m, smpte 344m and smpte 259m coaxial cable serial digital interfaces. GS9068A ? smpte 259m and smpte 344m coaxial cable serial digital interfaces. description the gs1528a/9068a is a second generation high-speed bicmos integrated circuit designed to drive one or two 75 co-axial cables. the gs1528a may drive data rates up to 1.485gb/s and provides two selectable slew rates in order to achieve compliance to smpte 259m, smpte 344m and smpte 292m. the GS9068A may drive data rates up to 540mb/s and will achieve compliance to smpte 259m and smpte 344m. the gs1528a/9068a ac cepts a lvpecl level differential input that may be ac coupled. external biasing resistors at the inputs are not required. power consumption is typically 168mw using a 3.3v power supply. the gs1528a/9068a is pb-free, and the encapsulation compound does not contain halogenated flame retardant. this component and all homogeneous subcomponents are rohs compliant.
gs1528a / GS9068A data sheet 30953 - 4 january 2006 2 of 16 gs1528a functional block diagram GS9068A functional block diagram sdo r set sdo sdi sdi sd/hd bandgap reference and biasing circuit output stage & control input differential pair sdo r set sdo sdi sdi bandgap reference and biasing circuit output stage & control input differential pair
gs1528a / GS9068A data sheet 30953 - 4 january 2006 3 of 16 contents features ....................................................................................................................... .1 applications................................................................................................................... 1 description .................................................................................................................... 1 1. pin out ..................................................................................................................... .4 1.1 gs1528a pin assignment ... .............. .............. .............. .............. ........... ........4 1.2 GS9068A pin assignment ... .............. .............. .............. .............. ........... ........4 1.3 gs1528a / GS9068A pin descriptions ...... .............. .............. .............. ...........4 2. electrical characteristics ...........................................................................................5 2.1 absolute maximum ratings ............................................................................5 2.2 dc electrical characteristics ............... ...........................................................5 2.3 ac electrical characteristics .............. .............................................................6 3. solder reflow profiles...............................................................................................7 4. input / output circuits ............................... ................................................................8 5. detailed description ..................................... .............................................................9 5.1 input interfacing ..............................................................................................9 5.2 output interfacing ...........................................................................................9 5.3 output return loss measurement ................................................................11 5.4 output amplitude adjustment .......................................................................12 6. application information............................................................................................13 6.1 pcb layout ...................................................................................................13 6.2 typical application circuits ...........................................................................14 7. package & ordering information .............................................................................15 7.1 package dimensions ....................................................................................15 7.2 packaging data .............................................................................................15 7.3 ordering information .....................................................................................15 8. revision history ......................................................................................................16
gs1528a / GS9068A data sheet 30953 - 4 january 2006 4 of 16 1. pin out 1.1 gs1528a pin assignment figure 1-1: 8 pin soic 1.2 GS9068A pin assignment figure 1-2: 8 pin soic 1.3 gs1528a / GS9068A pin descriptions sdi sdi v ee r set sdo sdo sd/hd v cc 1 2 3 4 8 7 6 5 gs1528a 8 pin soic top view sdi sdi v ee r set sdo sdo nc v cc 1 2 3 4 8 7 6 5 GS9068A 8 pin soic top view pin number name timing type description 1,2 sdi, sdi analog input serial digital differential input. 3v ee ? power most negative power suppl y connection. connect to gnd. 4r set analog input external output amplitude control resistor. 5v cc ? power most positive power supply connection. connect to +3.3v. 6 sd/hd non synchronous input gs1528a: output slew rate control. when set high, the output will meet smpte 259m rise/fall time specifications. when set low, the serial outputs will meet smpte 292m rise/fall time specifications. nc ? ? GS9068A: no connect. not connected internally. 7, 8 sdo , sdo analog output serial digital differential output.
gs1528a / GS9068A data sheet 30953 - 4 january 2006 5 of 16 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter value supply voltage -0.5v to 3.6 v dc input esd voltage 2kv storage temperature range -50c < t s < 125c input voltage range (any input) -0.3 to (v cc +0.3)v operating temperature range 0c to 70c solder reflow temperature 260c power dissipation 300mw v dd = 3.3v, t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units notes test levels supply voltage v cc ? 3.135 3.3 3.465 v 5% 3 power consumption p d t a = 25c ? 168 ? mw ? 5 supply current i s t a = 25c?5164ma?1 output voltage v cmout common mode ? v cc - v out ?v?6 input voltage v cmin common mode 1.6 + v sdi /2 ? v cc - v sdi /2 v ? 6 sd/hd input v ih ?2.4??v17 v il ???0.8v17 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing des ign/characterization data of similar product. 9. indirect test. notes: 1. this parameter applies only to the gs1528a.
gs1528a / GS9068A data sheet 30953 - 4 january 2006 6 of 16 2.3 ac electrical characteristics v dd = 3.3v, t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units notes test levels serial input data rate dr sdo gs1528a ? ? 1.485 gb/s 1 1 dr sdo GS9068A ? ? 540 mb/s ? 1 additive jitter ? 1.485gb/s ? 22 ? ps p-p 21 ? 270mb/s ? 16 ? ps p-p ?4 ? GS9068A ? 16 ? ps p-p ?1 rise/fall time t r , t f sd/hd =0 ? ? 220 ps 2, 3 1 t r , t f sd/hd =1 400 ? 800 ps 2, 3 1 t r , t f GS9068A 400 ? 800 ps 3 1 mismatch in rise/fall time u t r , u t f ???30ps?1 duty cycle distortion ? sd/hd =0 ? ? 30 ps 2 1 ? sd/hd =1 ? ? 100 ps 2 7 ? GS9068A ? ? 100 ps ? 1 overshoot ? sd/hd =0 ? ? 10 % 2 7 ? sd/hd =1 ? ? 8 % 2 1 ? GS9068A ? ? 8 % ? 1 output return loss orl ? 15 ? ? db ? 7 output voltage swing v out single ended into 75 external load r set = 750 750 800 850 mv p-p ?1 input voltage swing u v sdi differential 300 ? 2000 mv p-p ?7 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply an d temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. 9. indirect test. notes: 1. the input coupling capacitor must be set accordingly for lower data rates. 2. this parameter applies only to the gs1528a. 3. rise/fall time measured between 20% and 80%.
gs1528a / GS9068A data sheet 30953 - 4 january 2006 7 of 16 3. solder reflow profiles the device is manufactured with matte-sn te rminations and is compatible with both standard eutectic and pb-free solder re flow profiles. msl qualification was performed using the maximum pb-free reflow profile shown in figure 3-1 . the recommended standard pb reflow profile is shown in figure 3-2 . figure 3-1: maximum pb-free solder reflow profile (preferred) figure 3-2: standard pb reflow profile (pb-free package) 25?c 150?c 200?c 217?c 260?c 250?c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3?c/sec max 6?c/sec max 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max
gs1528a / GS9068A data sheet 30953 - 4 january 2006 8 of 16 4. input / output circuits figure 4-1: differential input stage (sdi/sdi ) figure 4-2: differential output stage (sdo/sdo ) i ref derived using r set figure 4-3: slew rate select input stage (gs1528a only) v cc v cc sdi sdi 10k 10k 5k 10k v cc i ref sdo sdo sd/hd v cc on chip reference
gs1528a / GS9068A data sheet 30953 - 4 january 2006 9 of 16 5. detailed description 5.1 input interfacing s di/sdi are high impedance differential inputs. the equivalent input circuit is shown in figure 4-1 . several conditions must be observed when interfacing to these inputs: ? the differential input signal amplitude must be between 300 and 2000mvpp. ? the common mode voltage range must be as specified in the dc electrical characteristics table . ? for input trace lengths longer than approximately 1cm, the inputs should be terminated as shown in the typical application circuit. the gs1528a/9068a inputs are self-biased, allowing for simple ac coupling to the device. for serial digital video, a minimu m capacitor value of 4.7f should be used to allow coupling of pathological test signals. a tantalum capacitor is recommended. sd/hd input pin (gs1528a only): the gs1528a sdo rise and fall times can be set to comply with both smpte 259m/344m and smpte 292m. for all smpte 259m standards, or any data rate that requires longer rise and fall time characteristics, the sd/hd pin must be set high by the application layer. for smpte 292m standards and signals which require faster rise and fall times, this pin should be set low. 5.2 output interfacing the gs1528a/9068a outputs are current mode, and will drive 800mv into a 75 load. these outputs are protected from accid ental static damage with internal static protection diodes. the smpte 292m, smpte 344m and smpte 259m standards require that the output of a cable driver ha ve a source impedance of 75 and a return loss of at least 15db between 5mhz and 1.485ghz. in order for an sdi output circuit using the gs1528a/9068a to meet this specification, the output application circuit shown in section 6.2 is recommended. the value of l comp will vary depending on the pcb layout, with a typical value of 5.6nh . a 4.7f capacitor is used for ac c oupling the output of the device. this value is chosen to ensure that pathological signals can be coupled without a significant dc component occurring. please see section 6.0 for more details.
gs1528a / GS9068A data sheet 30953 - 4 january 2006 10 of 16 figure 5-1: output signal for 270mb/s input figure 5-2: output signal for 1.485gb/s input (gs1528a only) the output protection diodes act as a varactor (voltage controlled capacitor) as shown in figure 5-3 . therefore, when measuring return loss at the gs1528a/9068a output, it is necessary to take the measurement for both a logic high and a logic low output condition. consequently, the output capa citance of the device is dependent on the logic state of the output. tek stopped: 8110 acquisitions tek running: normal
gs1528a / GS9068A data sheet 30953 - 4 january 2006 11 of 16 figure 5-3: static protection diodes 5.3 output return loss measurement to perform a practical return loss measurement, it is necessary to force the gs1528a/9068a output to a dc high or low condition. the actual measured return loss will be based on the outputs being static at v cc or v cc -1.6v. under normal operating conditions the outputs of the device swing between v cc -0.4v and v cc -1.2v, so the measured value of return loss will not represent the actual operating return loss. a simple method of calculating the values of actual operating return loss is to interpolate the two return loss measurements. in this way, the va lues of return loss are estimated at v cc -0.4v and v cc -1.2v based on the measurements at v cc and v cc -1.6v. the two values of return loss (high and lo w) will typically differ by several decibels. if the measured return loss is r h for logic high and r l for logic low, then the two values can be interpolated as follows: r ih = r h - (r h -r l )/4 and r il = r l +(r h -r l )/4 where r ih is the interpolated logic high value and r il is the interpolated logic low value. for example, if r h = -18db and r l = -14db, then the interpolated values are r ih = -17db and r il = -15db. sdo sdo gs1528a
gs1528a / GS9068A data sheet 30953 - 4 january 2006 12 of 16 5.4 output amplitude adjustment the output amplitude of the gs1528a/9 068a can be adjusted by changing the value of the r set resistor as shown in table 5-1 . for an 800mv p-p output with a nominal 7% tolerance, a value of 750 is required. a 1% smt resistor should be used. the r set resistor is part of the high speed output circuit of the gs1528a/9068a. the resistor should be placed as close as possible to the r set pin. in addition, the pcb capacitance should be minimized at this node by removing the pcb groundplane beneath the r set resistor and the r set pin. table 5-1: r set vs v od r set r ( ) output swing (mvp-p) 995 608 824 734 750 800 680 884 573 1040 note: for reliable operation of the gs1528a/9068a ov er the full temperature range, do not use an r set value below 573 .
gs1528a / GS9068A data sheet 30953 - 4 january 2006 13 of 16 6. application information 6.1 pcb layout special attention must be paid to component layout when designing serial digital interfaces for hdtv. an fr-4 dielectric can be used, however, controlled impedance transmission lines are required for pcb traces longer than approximately 1cm. note the following pcb artwork features used to optimize performance: ? the pcb trace width for hd rate signals is closely matched to smt component width to minimize reflection s due to changes in trace impedance. ? the pcb groundplane is removed under the gs1528a/9068a output components to minimize parasitic capacitance. ? the pcb ground plane is removed under the gs1528a/9068a r set pin and resistor to minimize parasitic capacitance. ? input and output bnc connectors are surface mounted in-line to eliminate a transmission line stub caused by a bn c mounting via high speed traces which are curved to minimize impedance variations due to change of pcb trace width.
gs1528a / GS9068A data sheet 30953 - 4 january 2006 14 of 16 6.2 typical application circuits figure 6-1: gs1528a typical application circuit figure 6-2: GS9068A typical application circuit sd/hd gs1528a 1 2 3 4 8 7 6 5 sdi sdi vee rset sdo sdo sd/hd vcc 10n 75 5.6n 4u7 bnc vcc 75 5.6n 10n 75 4u7 49.9 750 10n 49.9 4u7 75 bnc vcc 4u7 vcc * typical value varies with layout differential data input * * note: all resistors in ohms, capacitors in farads, and inductors in henrys, unless otherwise noted. GS9068A 1 2 3 4 8 7 6 5 sdi sdi vee rset sdo sdo vcc 10n 75 5.6n 4u7 bnc vcc 75 5.6n 10n 75 4u7 49.9 750 10n 49.9 4u7 75 bnc vcc 4u7 vcc * typical value varies with layout differential data input * * note: all resistors in ohms, capacitors in farads, and inductors in henrys, unless otherwise noted. nc
gs1528a / GS9068A data sheet 30953 - 4 january 2006 15 of 16 7. package & ordering information 7.1 package dimensions 7.2 packaging data 7.3 ordering information 0.49 max 3.81 0.05 3 spaces @ 1.27 0.05 4.0 max 6.20 max 0.25 max 1 8 1.91 max 4 5 1.27 max 0.25 max 5.00 max. 0.60 max = = = 8-pin soic all dimensions are in millimetre s parameter value package type 8-pin soic moisture sensitivity level 2 junction to case thermal resistance, j-c 72c/w junction to air thermal resistance, j-a (at zero airflow) 116c/w pb-free and rohs compliant yes part number package temperature range gs1528a gs1528ackae3 8-pin soic 0c to 70c GS9068A GS9068Ackae3 8-pin soic 0c to 70c
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nish i shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2004 gennum corporation. all rights reserved. printed in canada. www.gennum.com gs1528a / GS9068A data sheet 30953 - 4 january 2006 16 16 of 16 document identification data sheet the product is in production. gennum reserves the right to make changes to the product at any time wit hout notice to improve reliability, function or design, in order to provide the best product possible. 8. revision history version ecr pcn date changes and/or modifications 0 132954 february 2004 new document. 1 133654 june 2004 modified ac electr ical characteristics. added reflow profiles. upgraded from a preliminary data sheet to a data sheet. 2 137403 july 2005 updated to current document template to remove ?proprietary and confidential? footer. re-ordered solder reflow profiles to show preference for pb-free profile. clarified naming of standard pb solder reflow profile. added packaging data section. updated document to reflect the rohs compliance of both the gs1528a and GS9068A. 3 137886 september 2005 corrected process to bicmos. 4 139112 38124 january 2006 corrected input differential swing to 2200mv.

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